verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/tb2”---Testbench

1、题目2、分析照着时序图写testbench就行3、代码实现module top_module(); reg clk; reg in; reg [2:0]s; wire out; initial begin clk 1b0; in 1b0; s 3d2; #10 s 3d6; #10 begin s 3d2; in 1b1;end #10 begin s 3d7; in 1b0;end #10 begin s 3d0; in 1b1;end #30 in 1b0; end always #5 clk ~clk; q7 q7_inst(clk,in,s,out); endmodule4、结果